The present invention relates to an analog-to-digital converter, and particularly to a successive-approximation-type analog-to-digital converter.
A successive-approximation-type analog-to-digital converter (or a successive-approximation-type A/D converter) comprises a reference-voltage generating circuit and a comparison circuit. Herein, the reference-voltage generating circuit generates a reference voltage whose level is successively altered. The comparison circuit compares the reference voltage with an analog input, which is sampled and held, so as to determine the digit of each bit in the digital output to be produced by converting the analog input. FIG. 1 shows an example of the A/D converter. A sample-and-hold circuit (hereinafter, simply referred to as a S/H circuit) 1 receives an analog-input voltage from an input terminal 6 so as to sample and hold it. A digital-to-analog converter (hereinafter, simply referred to as a D/A converter or DAC) 2 is provided to generate the reference voltage. Either the output of the D/A converter 2 and the output of the S/H circuit 1 is applied to one terminal of a capacitor C1 through switches S.sub.1 and S.sub.2. Another terminal of the capacitor C.sub.1 is connected with an input terminal of an inverter I.sub.1. A switch S.sub.3 is connected in parallel with the inverter I.sub.1. All of the capacitor C.sub.1, the inverter I.sub.1 and the switch S.sub.3 are connected together to form a comparison circuit 3.
In FIG. 1, an output terminal of the inverter I.sub.1 is connected with a series circuit comprising a capacitor C.sub.2, an inverter 12, a capacitor C.sub.3, an inverter 13 and an inverter 14. The inverter 12 is connected in parallel with a switch S.sub.4, while the inverter 13 is connected in parallel with a switch S.sub.5. The reason why the multiple inverters are connected together is to obtain a sufficient gain which is required for performing a comparing operation with respect to a LSB voltage of the D/A converter 2 (where `LSB` is an abbreviation for `least significant bit`). An output of the inverter 14 is supplied to successive-approximation-conversion logic circuit (hereinafter, simply referred to as a logic circuit) 4. The logic circuit 4 produces data, representative of an essential element for the generation of the reference voltage, so that this data is supplied to the D/A converter 2. The logic circuit 4 further controls the switches S.sub.1 to S.sub.5.
The above-mentioned A/D converter can be configured by a CMOS-type IC (where CMOS is an abbreviation for `complementary metal-oxide semiconductor). In that case, all of the circuits in the A/D converter, except the S/H circuit 1, can be fabricated in one-chip IC. The D/A converter 2 can be configured by a resistor-string-type circuitry using the CMOS. As each of the switches S.sub.1 to S.sub.5, a CMOS switch is used. In addition, the capacitor can be configured by an oxidation film or the like in the IC chip.
One comparing operation to be effected between the output of the S/H circuit 1 and the output of the D/A converter 2 is performed in two cycles. In first cycle, all of the switches S.sub.1 S.sub.3, S.sub.4 and S.sub.5 are turned on, while the switch S.sub.2 is turned off. In this cycle, all of the inverters I.sub.1 to 13, each configured by the CMOS circuit, are shorted; hence, the same electric potential is applied to input and output terminals of the inverter and is equal to a half of the power-supply voltage VDD; in other words, the electric potential applied to the inverter is reset to center potential. Since the alternating signal is inputted to the circuitry shown in FIG. 1, the center potential is set at zero level. In this state, the output voltage of the D/A converter 2 is supplied to the capacitor C.sub.1 through the switch S.sub.1 so that the capacitor C.sub.1 is charged. In other words, the output potential of the D/A converter 2 is applied to one terminal of the capacitor C.sub.1, while the center potential, given by the inverter, is applied to another terminal of the capacitor C.sub.1.
In next cycle, the switches S.sub.1, S.sub.3, S.sub.4 and S.sub.5 are turned off, while the switch S.sub.2 is turned on. This enables each of the inverters I.sub.1 to 13 to perform an inverting operation. As a result, the output of tile S/H circuit 1 is supplied to the capacitor C.sub.1. If the output of the S/H circuit 1 is higher than the reference voltage, an input potential of the inverter I.sub.1 should be higher than the center potential. On the other hand, if the output is lower than the reference voltage, the input potential of the inverter I.sub.1 should be lower than the center potential. Thus, one of the digits `0` and `1` is selectively determined for each of the bits in the digital output in response to the level relationship between the input potential of the inverter I.sub.1 and the center potential.
Thereafter, the comparing operation, as described above, is repeatedly performed a certain number of times, the number of which corresponds to the number of the bits included in the digital output to be produced. Herein, the comparing operation is performed on the basis of the reference voltage whose level is successively altered.
In general, the A/D converter particularly used for the audio device is designed to produce the digital output of twelve bits to sixteen bits. Therefore, the D/A converter, which is equipped inside of the A/D converter, should be designed to receive the digital input of twelve bits to sixteen bits. Since a relatively large number of bits are required for the digital output produced by the A/D converter, it is required to realize an extremely high resolution for the comparison circuit. In addition, it is also requested to increase the conversion speed of the A/D converter. This is a contradictory situation for the A/D converter, because in the known A/D converter, a higher resolution may result in a lower conversion speed.
In the one-chip A/D converter, both of the analog signal and digital signal exist inside of the chip. This means that the noises, which may be produced by the digital circuit, are easy to be transferred to the analog circuit. In addition, the comparison circuit 3 should have a relatively large gain; hence, the comparison circuit 3 is easily affected by the noises. In order to reduce a bad effect of the noises, the capacity of each of the capacitors C.sub.1 to C.sub.3 should be increased to be larger than a certain degree of capacity so that the impedance will be decreased. Among those capacitors, especially the capacitor C.sub.1 should be increased in the capacity, because this capacitor C.sub.1 deals with the signal whose level is the smallest.
However, the conversion speed depends upon the time which is required for charging the capacitor C.sub.1 by the D/A converter 2. Since the D/A converter 2 has a limited output impedance, an increase in the capacity of the capacitor C.sub.1 results in a decrease in the conversion speed of the A/D converter.
In short, it is difficult for the integrated A/D converter to simultaneously realize the improvement in the resolution and S/N ratio as well as the increase of the conversion speed.
FIG. 2 shows another example of the successive-approximation-type A/D converter. In FIG. 2, an analog input is supplied to a sample-and-hold circuit (i.e. ,S/H circuit) 11 which performs sample-and-hold operations. Thus, each of the instantaneous values sequentially produced from the S/H circuit 11 is supplied to a comparator 12. The comparator 12 compares the instantaneous value with an output (i.e., an analog output) of a D/A converter 13. The D/A converter 13 receives four-bit data consisting of four bits M0, M1, M2 and M3, wherein `M0` corresponds to the most significant bit (i.e., MSB) and `M3` corresponds to the least significant bit (i.e., LSB). The four-bit data is produced by a successive-approximation circuit 14 on the basis of an output of the comparator 12.
The successive-approximation circuit 14 contains a four-bit successive-approximation register (i.e.. 4-bit SAR) and a control circuit (not shown). The control circuit changes each of the digits of the bits M0 to M3 in a manner as shown in FIG. 3B in response to the output of the comparator 12 which has the digit `0` or `1`. As shown in FIG. 3A, the comparator 12 performs the comparing operation at each of four moments t1, t2, t3 and t4. At first moment t1, the digit 1 is set to the most significant bit `M0` only, so that the D/A converter 13 produces an analog output whose level corresponds to the four-bit data `1000`. This analog output is supplied to the comparator 12. Hence, the comparator 12 compares the analog output with the instantaneous value of the analog input.
In the graph of FIG. 3A, a height of the bar represents the level of the analog output of the D/A converter 13 at each moment. At the moment t1, the level of the analog output is greater than the instantaneous value of the analog input. Therefore, the control circuit Judges that the digit 1 set to the bit `M0` is not appropriate. At this time, the comparator 12 produces the output having the digit 0. Hence, under the control of the control circuit, the digit 0 is set to the bit M0 at the next moment t2, while the digit 1 is set to the bit M1 only. Thus, the D/A converter 13 produces the analog output on the basis of the four-bit data `0100`. Then, the comparator 12 performs the comparing operation with respect to this analog output.
At the moment t2, the instantaneous value of the analog input is greater than the level of the analog output. Therefore, at the moment t3, the control circuit increases the four-bit data to the data `0110`. Then, the comparing operation is performed again. As described heretofore, the comparing operation is successively performed. Thus, finally, it is possible to obtain the analog output of the D/A converter 13, the level of which is tile closest to the instantaneous value of the analog input. Based on the final analog output, the A/D converter shown in FIG. 2 will produce the final digital output. Since the A/D converter shown in FIG. 2 is configured as the four-bit converter, the comparing operation is repeatedly performed four times. Thus, the analog output of the D/A converter 13 at the final moment t4 will be converted into the final digital output of the A/D converter.
Generally speaking, in the successive-approximation-type A/D converter as well as the normal A/D converters, the precision of conversion and the limit of the S/N ratio depend upon the internal noise which occurs in the conversion system of the A/D converter. For example, when the noise is introduced into the comparator at the timing to perform the comparing operation, this noise greatly affects the output of the A/D converter. Such problem is easily created in the monolithic LSI. In the monolithic LSI, both of the analog circuit and digital circuit are integrated; in other words, the A/D converter is fabricated on the same substrate together with the other digital circuits. The reason why the above-mentioned problem is easily created in the monolithic LSI is that the noise from the digital system frequently dominates (or greatly affects) the noise of the A/D converter.